应届毕业生
硕士
最近更新
1320人关注
职位描述
该职位还未进行加V认证，请仔细了解后再进行投递！
职责描述:
1. Full layout design for standard cell/IO/SRAM IPs in advanced process nodes
2. Work on the physical verification (DRC/LVS/Antenna ...)
3. Work on test chip layout design and verification
4. Close cooperation with designers on PPA optimization
任职要求:
1. At least BS Degree of Microelectronics or Physics.
2. Excellent graduate or at least 1 years' related working experience
3. Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)
4. Familiar with design rule and layout effect in advanced process.
5. Excellent skills of communication and teamwork are also expected.
6. Programming experience (Perl/tcl skill) will be a plus.
7. Experience in advanced process (n16 and beyond) will be a plus.
截止日期：2025年09月05日
注：联系我时，请说是在海沧人才网上看到的。
工作地点
地址：南京江宁区南京-江宁区九龙湖
求职提示：用人单位发布虚假招聘信息，或以任何名义向求职者收取财物（如体检费、置装费、押金、服装费、培训费、身份证、毕业证等），均涉嫌违法，请求职者务必提高警惕。
职位发布者
刘先生HR
台积电(南京)有限公司
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电子技术·半导体·集成电路
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200-499人
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外商独资·外企办事处
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浦口经济开发区紫峰路16号
