应届毕业生
硕士
最近更新
4382人关注
职位描述
该职位还未进行加V认证，请仔细了解后再进行投递！
职责描述:
1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2. Design flow/methodology development and innovation for front-end design challenges.
3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任职要求:
1. MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2. 3 years working experience.
3. Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4. Familiar with tcl/Perl/Python program.
注：联系我时，请说是在海沧人才网上看到的。
工作地点
地址：南京江宁区南京-江宁区台积电(南京)有限公司
求职提示：用人单位发布虚假招聘信息，或以任何名义向求职者收取财物（如体检费、置装费、押金、服装费、培训费、身份证、毕业证等），均涉嫌违法，请求职者务必提高警惕。
职位发布者
HR
台积电(南京)有限公司
-
电子技术·半导体·集成电路
-
200-499人
-
外商独资·外企办事处
-
浦口经济开发区紫峰路16号
